The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping.
In conventional PC server arrangements, local area network (LAN) adapters reside directly under a peripheral component interconnect (PCI) bus attached to the microprocessor.
New requirements are presented in a PC server arrangement where LAN adapters do not reside directly under a peripheral component interconnect (PCI) bus attached to the microprocessor, for example, instead residing behind separate buses under multiple PCI to PCI bridges. The PCI rules require that the adapter interrupt signal from behind a PCI to PCI bridge be routed to one of the signals INT A, INT B, INT C or INT D based on the PCI device number. Also it is desirable that PCI interrupts are not shared among multiple I/O adapters.
In order for the PC to map the adapters to known Interrupts and to have the LAN adapters always appear as constant known Bus/Device Numbers, a configurable way of having the device appear at a known location on the PCI bus is required. A need exists for an improved method and apparatus for interrupt routing of peripheral component interconnect (PCI) adapters.
A principal object of the present invention is to provide a method and apparatus for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. Other important objects of the present invention are to provide such a method and apparatus for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. A first processor complex includes a multifunction PCI to PCI bridge interface chip. A first local PCI bus is coupled between a second processor complex and the multifunction PCI to PCI bridge interface chip. A second host PCI bus is coupled between the multifunction PCI to PCI bridge interface chip and a second multifunction PCI to PCI bridge chip. A plurality of peripheral component interconnect (PCI) adapters are coupled to the second multifunction PCI to PCI bridge chip. The multifunction PCI to PCI bridge interface chip of the first processor complex includes interrupt mapping logic for mapping interrupts from the PCI adapters to PCI interrupts on the local PCI bus to the second processor complex.
In accordance with features of the invention, the multifunction PCI to PCI bridge interface chip of the first processor complex includes translation logic for translating a configuration cycle on the first local PCI bus from the second processor complex to another configuration cycle on the second host PCI bus and for translating a configuration cycle on the second host PCI bus from the PCI adapters to another configuration cycle on the first local PCI bus to the second processor complex. The multifunction PCI to PCI bridge interface chip of the first processor complex includes a bus number register for specifying a PCI bus number and a device translation register for specifies a translation value for each function of the multifunction PCI to PCI bridge interface chip for determining a device number of each of the plurality of PCI adapters.